Forum Discussion
Do you able to solve the issue? Do you need further help?
No, the issue remains unresolved. Yes definitely.
- RichardT_altera6 years ago
Super Contributor
Could you help to share your design? A simplified design that can duplicate the error is sufficient.
- RichardT_altera6 years ago
Super Contributor
1) You may have an invalid filename that you are trying to pass to vcom, eg.,
vcom c:/vhdl/my_vhdl_file.vhd
would work, but
would not, since the backslash is a Tcl escape character, but
vcom {c:\vhdl\my_vhdl_file.vhd}
will work, since it passes the path without interpreting the contents of {}
2) You might also look for spaces in your paths. They can be used, but you have to use "" or {} to pass the path as a "single string".
- tessellation5 years ago
New Contributor
I had this or a similar problem trying to simulate IP cores with a Quartus Lite project in ModelSim. I am used to using Quartus Pro where you just generate a simulator setup script using that function under tools. However, that is not available with Quartus lite.
So there are base IP cores like counters, fifo and rom that don't create a .tcl file when they are generated. For these you just need to add a vcom for them in your .tcl or .do file.
For IP cores like fft and fir they do generate a .tcl file. Look in their simulation -> mentor folder and you will find it. Copy that .tcl and the whole simulator folder to you main project directory. With the .tcl in your main directory uncomment/fill in the appropriate lines, including vcom of the base IP cores.
Then you can just source <your tcl file>.tcl in model sim.
Hope this helps someone out there.