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Well , I mean for example if im designing an adder , thats fully combinational design which needs no clock , but to get appropriate timing analysis I have to make it work with clock like latch the operands into registers and latch the output . Im asking if there is some other way in which I can give up the clock and just get the latency between the inputs and output of the adder?
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That is rtl we are talking about. combinatorial clouds sandwiched between registers. TQ takes care of delays as comb decisions are sampled at clock edge. if it passes timing you don't need to see delay values.
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