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Altera_Forum
Honored Contributor
Honored ContributorSimulation of timing analysis in ModelSim-Altera ??!!!
Hey guys , this is my first time to use the ModelSim-Altera analysis tool. I followed many tutorials and I know how to set the parameters of the TimeQuest and I get correct compilation of the TimeQue...
Altera_ForumHonored Contributor
Honored Contributor --- Quote End --- Can you explain that. All fpga designs are based on rtl. Unless you are doing some unusual cpld work. Delays may vary from build to build. --- Quote End --- Well , I mean for example if im designing an adder , thats fully combinational design which needs no clock , but to get appropriate timing analysis I have to make it work with clock like latch the operands into registers and latch the output . Im asking if there is some other way in which I can give up the clock and just get the latency between the inputs and output of the adder?
