--- Quote Start ---
Thx Kaz , So u mean I do not need to check timing on waveforms if the TQ is giving correct results ?
--- Quote End ---
Provided your constraints are correct.
--- Quote Start ---
I still need to see the exact timing simulation on waveforms ? so what would u suggest ?
--- Quote End ---
.
TQ takes care of delays and should be hidden from you unless you are having timing failures.
For timing sim you add delay file to modelsim (called sdf if vhdl design) and when you open sim you add that file by clicking add.
Alternatively old quartus sim had a handy timing simulator.
--- Quote Start ---
Another question is if I try design a fully combinational circuit , how do i get the timing analysis results (Max latency between Inputs and outputs) if i do not have any clocks ?
--- Quote End ---
Can you explain that. All fpga designs are based on rtl. Unless you are doing some unusual cpld work.
Delays may vary from build to build.
Honored Contributor
