Simulation in Quartus 10

Write a tesbench.

You've to set the Settings.. | simulation in order to compile the testbench.

An example, combinatorial, testbench is the for a priority encoder following (remove line numbers):

1 `timescale 1ns/1ps // define simulation time units

2 module prenc83_tb(); // module with no inputs or outputs

3 reg [7:0] Atb; // reg net type. To be assigned in the initial block

4 wire [2:0] Ytb;

5 wire idle;

6 prenc83 d1(.A(Atb),.Y(Ytb)); // UUT named d1

7 initial // Just once at the beginning of the simulation

8 begin

9 Atb = 8'h01; // Eight bits hexadecimal value

10 # 100; // 100 time units delay -> 100 ns

11 Atb = 8'h02;# 100;

12 Atb = 8'h04;# 100;

13 Atb = 8'h08;# 100;

14 Atb = 8'h10;# 100;

15 Atb = 8'h20;# 100;

16 Atb = 8'h40;# 100;

17 Atb = 8'h80;# 100;

18 Atb = 8'h44;# 100;

19 Atb = 8'hF0;# 100;

20 Atb = 8'h00;# 100;

21 Atb = 8'hCF;# 100;

22 $stop; // System call that stops the simulation

23 end

24 endmodule

For a sequential project you need a clock.

It can be defined, in the testbench, as:

// Generates the clock waveform

parameter PERIOD=20;

always

begin

CLKtb=0;# (PERIOD/2.0); // Delays by PERIOD/2 time units

CLKtb=1;# (PERIOD/2.0);

end