Altera_Forum
Honored Contributor
11 years agoSimulating a QSYS system featuring a HPS
Hello,
I'm developing a QSYS system to transmit data via LVDS. Within this module there are the common blocks of a qsys system with a processor, namely memory, jtag, HPS, parallel IOs etc. There is also a custom module in there. The simulation model for this custom module is the same as the synthesis model. In QSYS, after creating the QSYS testbench system and compiling it, I run ModelSim Starter Edition to run the generated tcl script in the mentor/ directory, Everything compiles well, but while elaborating many warnings appear, and most are related to systemverilog files auto-generated by QSYS. A fatal error concludes the elaboration, elaborating nothing. What am I doing wrong? I know it might not be possible to simulate a QSYS system in ModelSim Starter Edition, but is there any way I can simulate the system I've got? regards