Altera_Forum
Honored Contributor
15 years agoSimulate Error in Modelsim
Hi all,
I got an error when simulating these files: Example.vmodule MyAdd(Co,Ci1,Ci2);
input Ci1,Ci2;
output Co;
assign C0=Ci1&Ci2;
endmodule Testbench_MyAdd.v module Testbench_MyAdd();
reg A, B;
wire Y;
parameter time_out = 200;
MyAdd(Y, A, B);
initial $monitor("A=%b, B=%b, C=%b", A, B, Y);
initial# time_out $finish;
initial begin
# 30 A = 0; B = 0;
# 30 A = 0; B = 1;
# 30 A = 1; B = 0;
# 30 A = 1; B = 1;
end
endmodule and the error is: # ** Error: (vsim-3037) D:/altera/10.1/Projects/ModelSim/Testbench_MyAdd.v(5): Missing instance name in instantiation of 'MyAdd'.# Region: /Testbench_MyAdd Anyone can help me resolve this issue?