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Honored Contributor
Honored ContributorSimulate Error in Modelsim
Hi all, I got an error when simulating these files: Example.v module MyAdd(Co,Ci1,Ci2);
input Ci1,Ci2;
output Co;
assign C0=Ci1&Ci2;
endmodule Testbench_MyAdd.v mod...
Altera_ForumHonored Contributor
Honored ContributorIt looks like that you only have your module name in line 5 of your testbench, you need to add an instance name (e.g. U1) after the module name, that looks like below.
count16 U1 ( .count(cnt_out),...);
