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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simulate Error in Modelsim

Hi all, I got an error when simulating these files: Example.v module MyAdd(Co,Ci1,Ci2); input Ci1,Ci2; output Co; assign C0=Ci1&Ci2; endmodule Testbench_MyAdd.v mod...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It looks like that you only have your module name in line 5 of your testbench, you need to add an instance name (e.g. U1) after the module name, that looks like below.

count16 U1 ( .count(cnt_out),...);