--- Quote Start ---
module check(clk,in,out);
input clk;
input signed [15:0] in;
output [15:0] out;
reg signed [15:0] out;
always @ (posedge clk) //negedge
if (in >= 500)
out <= 500;
else if (in <= -500)
out <= -500;
else
out <= in;
endmodule
--- Quote End ---
Hopefully code will work now. ( too simple,isn't it? )
Problem :confused: : Operation was being performed as an unsigned one which is not your
requirement, it was performing 2's complement and then was
comparing.
Solution :cool: : Declared signals as " signed" and make value as signed "500 or 16'sd500"
( instead of 16'd500 ) right for comparison.
Note : Never give keyword name for declaring identifiers. :)
Honored Contributor
