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Altera_Forum's avatar
Altera_Forum
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13 years ago

Simple Verilog Question--Impossible?

I have a verilog file Intensifier.v. In it is a module with the following port list: module Intensifier ( clk, _reset, intensifierInput, intensifierOutpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

How to implement this condition in verilog??

If input>500------> output= 500

If input<-500-----> output=-500

else --------------> output=input

This is my code for this:

module check( clk,input,output);

input clk;

input [15:0] input;

output [15:0] output;

reg [15:0] output;

always@(posedge clk) //negedge

if (input >= 16'h01f4)

output <= 16'h01f4;

else if (input <=16'hfe0c)

output <= 16'hfe0c;

else

output <= input;

endmodule

I don't known why i get wrong result!!!

Need for helping!!