Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSimple Verilog Question--Impossible?
I have a verilog file Intensifier.v. In it is a module with the following port list: module Intensifier ( clk, _reset, intensifierInput, intensifierOutpu...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- wire [1023:0] mainTestIn; //wire or reg wire [1023:0] mainTestOut; //wire or reg genvar i; generate for ( i=0; i<1023; i=i+1 ) begin Intensifier inst_i ( .clk ( clk ), ._reset ( _reset ), .intensifierInput ( mainTestIn ),
.intensifieroutput ( maintestout ) ); end endgenerate --- Quote End --- I think,you want like this.
