Simple Verilog Question--Impossible?

When I need to do this in VHDL, I use a for-generate statement. See if you can find the appropriate syntax for Verilog (or SystemVerilog).

Here's what it would look like in VHDL:

  -- Some of these would probably be top-level ports ...
  signal _reset : std_logic;
  signal clk : std_logic;
  signal intensifierInput : std_logic_vector(1023 downto 0);
  signal intensifierOutput : std_logic_vector(1023 downto 0);
...
  g1: for i in 0 to 1023 generate
 
       u1: intensifier
       port map (
           clk => clk,
           _reset => _reset,
           intensifierInput => intensifierInput(i),
           intensifierOutput => intensifierOutput(i)
       );
  end generate;

The syntax should be pretty similar. Do a search for generate in the Altera sopc_builder/ folder. I know I've seen examples in the Altera verilog code.

Cheers,

Dave