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Altera_Forum's avatar
Altera_Forum
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12 years ago

Simple State Machine Problem

Hi,

I attach a basic four state machine project file built with schematic and state machine wizard via Quartus 2 sp2.

Its basic operation theoretically must follow this table below:

sentido = 0; enable = 0; state = Scurr

sentido = 0; enable = 1; state = Sn-1

sentido = 1; enable = 0; state = Scurr

sentido = 1; enable = 1; state = Sn+1

Scurr = current state

The states are:

s0 (Q1 = 1; Q0 = 1),

s1 (Q1 = 1; Q0 = 0),

s2 (Q1 = 0; Q0 = 0),

s3 (Q1 = 0; Q0 = 1),

My Cyclone II FPGA Starter Board is not showing the LEDG[1] and LEDG[0] leds alternating their values at 1,49 Hz according to my SW[1] and SW[0] switches states ("10" or "00"). "sentido" in portuguese is equal to "direction".

Any idea why this project file doesn´t produce the desired outputs?

Regards

Jaraqui

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Just a comment: the website forbidds .rar attachments. So I renamed this file to a .zip one. The original is .rar. It can be unzipped without problems.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You have a bad connection in your schematic on LEDG1. Probably this cause the problem.

    There is something that doesn't look good in the state register description. You mix the asynchronous reset with the next state logic of the state machine:

    IF (reset='0') THEN

    reg_fstate <= s0;

    reg_Q1 <= '0';

    reg_Q0 <= '0';

    ELSE

    reg_Q1 <= '0';

    reg_Q0 <= '0';

    ...

    The orthodox way is:

    PROCESS (clock,reg_fstate,reg_Q1,reg_Q0)

    BEGIN

    IF (reset='0') THEN

    reg_fstate <= s0;

    reg_Q1 <= '0';

    reg_Q0 <= '0';

    ELSIF (clock='1' AND clock'event) THEN

    fstate <= reg_fstate;

    Q1 <= reg_Q1;

    Q0 <= reg_Q0;

    END IF;

    END PROCESS;

    PROCESS (fstate,reset,sentido,enable)

    BEGIN

    reg_Q1 <= '0';

    reg_Q0 <= '0';

    CASE fstate IS

    WHEN s0 =>

    IF (((sentido = '1') AND (enable = '1'))) THEN

    reg_fstate <= s1;

    ...

    The last thing. You design a clock divider. This is not the best way to slow a clock. Altera and Quartus can implement it but can lead to timing problems in more complex design. The prefered way is with clock enables.

    ¡Éxitos!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Dear bertulus,

    Thank you for your precise comments and recommendations.

    I will post the modifications and the respective results obtained afterwards.

    Best regards,

    Jaraqui