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Altera_Forum
Honored Contributor
Honored ContributorSimple State Machine Problem
Hi, I attach a basic four state machine project file built with schematic and state machine wizard via Quartus 2 sp2. Its basic operation theoretically must follow this table below: ...
Altera_ForumHonored Contributor
Honored ContributorYou have a bad connection in your schematic on LEDG1. Probably this cause the problem.
There is something that doesn't look good in the state register description. You mix the asynchronous reset with the next state logic of the state machine: IF (reset='0') THEN reg_fstate <= s0; reg_Q1 <= '0'; reg_Q0 <= '0'; ELSE reg_Q1 <= '0'; reg_Q0 <= '0'; ... The orthodox way is: PROCESS (clock,reg_fstate,reg_Q1,reg_Q0) BEGIN IF (reset='0') THEN reg_fstate <= s0; reg_Q1 <= '0'; reg_Q0 <= '0'; ELSIF (clock='1' AND clock'event) THEN fstate <= reg_fstate; Q1 <= reg_Q1; Q0 <= reg_Q0; END IF; END PROCESS; PROCESS (fstate,reset,sentido,enable) BEGIN reg_Q1 <= '0'; reg_Q0 <= '0'; CASE fstate IS WHEN s0 => IF (((sentido = '1') AND (enable = '1'))) THEN reg_fstate <= s1; ... The last thing. You design a clock divider. This is not the best way to slow a clock. Altera and Quartus can implement it but can lead to timing problems in more complex design. The prefered way is with clock enables. ¡Éxitos!
