simple pin to pin delay managing in Cyclone

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This is not something you can guarantee at all through an FPGA - it will be affected by process, voltage and temperature fluctuations. Timequest will only ever give you a worst case estimate, never an exact figure.

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Ok I understand, imagine temperature and voltage fluctuations are stables and are not going to be problem...

I simple want to know how can I constraint a couple of input to output convinational pins doing a bypass function and, to be more clear, not related between them for any function.

That what I want to know is how to constraint "exactly" the delay of each couple (input to output) or if it could be possible the delay of both couples intended as a group.

But as a note: take into account, here, there is no reference clock.

Thanks

Jordi