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Altera_Forum
Honored Contributor
Honored Contributorsigned/unsigned multipliers
I can't seem to find a way to instantiate a multiplier that will dynamically select between signed and unsigned multiplication. This is on a Cyclone II, but applies to other parts as well.
Reading the Cyclone II documentation it is clear that signa, signb inputs does what I want, but none of the multipliers created with the Wizzard exports that as an input signal. Trying to infer it with the code below doesn't work (bug in Quartus II?); it complains that no logic depends on input_sign. However looking at the RTL with Tools/Netlist Viewers/RTL Viewer clearly shows it being used, however the technology map viewer shows input_sign as disconnected and signa and signb hardwired to ground. This looks like a bug to me, but I could be doing something wrong.
module mult(input clock,
input input_sign,
input input_a,
input input_b,
output reg output_c);
reg a, b;
reg sign;
always @(posedge clock) begin
sign <= input_sign;
a <= input_a;
b <= input_b;
if (sign)
output_c <= $signed(a) * $signed(b);
else
output_c <= $unsigned(a) * $unsigned(b);
end
endmodule
42 Replies
Altera_Forum--- Quote Start --- let us assume the numbers are signed: 111 * 011 (as signed I expect the result to be -1 * 3 = -3 now sign extend according to tricky's trick: 111 111 * 000 011 the verdict: = 10111101 and means -128 + 61 and /= the expected -3 So what is going on Now? --- Quote End --- you're forgetting that the result is only 6 bits because you had 2 x3 bit inputs. you ignore bits 6 and 7 (only bits 0-5 are valid)- Altera_Forum--- Quote Start --- You have chosen an example that works. Now consider this: I want to multiply these two 3 bit values through same unsigned multiplier: 111 * 011 = ? if viewed as unsigned, implies 7 * 3 = 21 [10101 correct] if viewed as signed, implies -1 * 3 and should give -3 [ but 10101 is wrong now, means -11] I don't know what you mean by sign extension here but let us try one bit extension: 0 111 * 0 011 7 * 3 = 21 0000 0000 10101 correct 1 111 * 0 011 15* 3 = 45 i.e. 101101 i.e./= -3 Correct ?, Wooooooo --- Quote End --- Let me correct myself, I got a bit flakey with numbers let us assume the numbers are signed: 111 * 011 (as signed I expect the result to be -1 * 3 = -3 now sign extend according to tricky's trick: 111 111 * 000 011 the verdict: = 10111101 and means -128 + 61 and /= the expected -3 So what is going on Now?
- Altera_Forum
Just to be clear:
0x1FF x 0x1FF becomes 0x001FF x 0x001FF for unsigned 0x3FFFF x 0x3FFFF for signed before any calculation is done. - Altera_Forum--- Quote Start --- They are available in MegaFunction, see my previous post. Regarding the sign extension point, I don't see that it works without additional logic, provided, that the full multiplier resolution (e.g. 9x9 = 18) with Cyclone hardware multipliers shall be utililzed. As an example 0x1ff * 0x1ff should have a result of 0x3ffff (-1) in signed arithmetic and 0x3fc01 (261121) in unsigned. --- Quote End --- Whoops: -1 x -1 = 1 0x1FF x 0x1FF = 0x3F801 when unsigned and 0x00001 when signed
- Altera_Forum--- Quote Start --- I still don't understand why signa and signb aren't available though. --- Quote End --- They are available in MegaFunction, see my previous post. Regarding the sign extension point, I don't see that it works without additional logic, provided, that the full multiplier resolution (e.g. 9x9 = 18) with Cyclone hardware multipliers shall be utililzed. As an example 0x1ff * 0x1ff should have a result of 0x3ffff (-1) in signed arithmetic and 0x3fc01 (261121) in unsigned.
- Altera_Forum
its just the standard 2's compliment rules. -ve numbers are just the same as the unsigned upper range.
The signa/b inputs will simply be to sign extend the inputs to the hardware multiplier. Using an appropriate type (signed/unsigned in VHDL) should get these turned on/off by the synthesisor. But if you're not on the limit of the length of input (18x18 for most FPGA multipliers) you can manual sign extend up to the 18 bit limit and then ignore the top bits from the 36 bit result to get the correct answer. - Altera_Forum
Well, so far so good even with 1 bit extension...edit(no I was wrong in my numbers)
You really know the tricks tricky ! Is this proven over whole range of values? Where did you get it from? Anyway, the problem of resizing inputs is not that attractive because you are going say from 8x8 mult to 16x16 , no way...if 9x9 also means 16x16 given the current mult grain - Altera_Forum
you have to sign extend the inputs to the length of the output.
so for 2 4 bits inputs you get an 8 bit result. The sign extension has to go on for the full 8 bits (ie. treat the inputs as 8 bits) - Altera_Forum
I just did my extesion correctly..see above post
- Altera_Forum--- Quote Start --- Am I missing something? --- Quote End --- Yes. You need to sign extend 111 to 111111 so -1 x 3 =
Sign extension just means take the MSB and keep adding it to the front to the input up to the length of the result. Unsigned numbers are really signed numbers with an implied '0' sign bit11 + 11 + 11 + 11 + 11 +11 -------- 111101 = -3
