Not commenting at all on the logistics of signed/unsigned multiplications, but more on synthesizable code, if you write:
signal sum : signed(3 downto 0);
IF(inc = '1') THEN
sum <= sum + 1;
ELSIF(dec = '1') THEN
sum <= sum - 1;
ELSE
sum <= sum;
END IF;
It will usually generate two adders and then mux the output together. However, if you were to write:
signal inc : integer range -1 to 1;
signal sum : signed(3 downto 0);
inc <= -1 when dec = '1' else
1 when inc = '1' else
0;
sum <= sum + inc;
Then it will usually generate a single adder with a mux at one of the input ports.
Obviously the summation should be in a clocked process, but i am being lazy.
Just a thought.
Kevin