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Altera_Forum's avatar
Altera_Forum
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8 years ago

[SignalTap] why signals are synthesized out when SignalTap enabled?

Hi All, I've met the strange phenomena - when I use the SignalTap-II instance (enable the SignalTap in Project Settings), it throws out some ports/nets in my design! It throws out exactly the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Are you referring to jtag ports/net created after adding stp file to design?

Signal-Tap uses memory and LEs to establish scan like structure to tap the net/signal required from design and pass it down to the jtag protocol, Which is used for establishing the communication between the fpga and quartus signal tap GUI.

because of this you may see the jtag ports.

disabled signal-tap and remove the stp file from file directory and check.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14678 https://www.alteraforum.com/forum/attachment.php?attachmentid=14679

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)