SignalTap issue with lpm_mult dataa bits

Here is the .vhd for the lpm_mult megafunction I am using:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.all;

ENTITY multlpm IS

PORT

(

clock : IN STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END multlpm ;

ARCHITECTURE SYN OF multlpm IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);

SIGNAL sub_wire1_bv : BIT_VECTOR (15 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);

COMPONENT lpm_mult

GENERIC (

lpm_hint : STRING;

lpm_pipeline : NATURAL;

lpm_representation : STRING;

lpm_type : STRING;

lpm_widtha : NATURAL;

lpm_widthb : NATURAL;

lpm_widthp : NATURAL

);

PORT (

clock : IN STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END COMPONENT;

BEGIN

sub_wire1_bv(15 DOWNTO 0) <= "0000000001100100";

sub_wire1 <= To_stdlogicvector(sub_wire1_bv);

result <= sub_wire0(31 DOWNTO 0);

lpm_mult_component : lpm_mult

GENERIC MAP (

lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",

lpm_pipeline => 1,

lpm_representation => "SIGNED",

lpm_type => "LPM_MULT",

lpm_widtha => 16,

lpm_widthb => 16,

lpm_widthp => 32

)

PORT MAP (

clock => clock,

dataa => dataa,

datab => sub_wire1,

result => sub_wire0

);

END SYN;

I guess I was reading the wrong nodes in SignalTap. I found the correct input nodes that only show 16 bits.

Thank you all for your help.