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Honored Contributor
Honored ContributorSignal Tap II Input Excitation
Hey guys, I have a Verilog DSP core that is fully functional. I would like to implement it into an FPGA and test it. To monitor the outputs I plan to use the Si...
Altera_ForumHonored Contributor
Honored ContributorThanks for the reply Dave. I considered using a similar setup, but instead I would use two memory components that were auto initialized. I would then write some verilog to control the memory, and then I would use Signal Tap II/Matlab to read the output.
I really don't want to create any additional memory or Verilog. I would like to just tie the inputs directly to the jtag some kind of way, and then let MATLAB communicate with it. But it seems that the Altera designers never included such a feature.