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Altera_Forum's avatar
Altera_Forum
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7 years ago

Signal Tap effects design / state machine behavior on an Arria 10

Hi All, So I am currently having an issue with a design that interfaces the EMIF IP block on an Arria 10. In simple terms data is captured in clock domain A, passes through a FIFO into the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

What signals are you tapping in Signal Tap? Are you using the clock provided by the IP for clocking your user logic (the state machine)?

Yes, this seems like it would be tricky to debug. You might need to simulate the design.