Forum Discussion
xianghua_li
New Contributor
New ContributorSignal bvalid of Agilex HPS is too slow when Rtile BAM writes to CCU through f2h_bridge
Following document [Intel Agilex® 7 FPGA I-Series PCIe Root Port Reference Design | Documentation | RocketBoards.org] (Intel Agilex® 7 FPGA I-Series PCIe Root Port Reference Design | Documentation | ...
Jeet14
Frequent Contributor
Frequent ContributorHi,
I think this can be improved based on the DDR refresh time and changing the mode to F2SDRAM (directly route packet to SDRAM not through CCU).
Regards
Tiwari
