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Altera_Forum
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12 years ago

Shifted clock signal when connecting to FPGA (cyclone iii)

Hello, I am getting some strange behavior that I can't understand what would be causing the behavior. I have a 32MHz crystal oscillator that I've been trying to use as a digital clock signal to drive...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you for your reply. Could you direct me to a handbook/user guide on how to use the pll properly (or global clock) that is generated via a dedicated input clock pin? I looked into the Timing Wizard in Quartus but I wasn't sure if this is where to look to generate the PLL output.