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Altera_Forum
Honored Contributor
Honored ContributorShifted clock signal when connecting to FPGA (cyclone iii)
Hello, I am getting some strange behavior that I can't understand what would be causing the behavior. I have a 32MHz crystal oscillator that I've been trying to use as a digital clock signal to drive...
Altera_ForumHonored Contributor
Honored ContributorLogic generated clocks are not recommended and liable to being rubbish. You should use a pll as you have much more control over the generated clock. Logic clocks can be affected by things like routing delays and temperature, which you have little control over.
