Shift Register

Hi!

I am just trying to generate a shift register in verilog. Quartus 9.1sp2 provides me with an error message I don't understand:

"Error (10198): Verilog HDL error at stratixIII_3sl150_dev_niosII_standard.v(246): part-select direction is opposite from prefix index direction"

Any clues what I am doing wrong?

Code: (Line marked with * is where the error is reported)

//number of FFs 
`define WIDTH 10
module sreg(
<snip>
  
   //-**************************************************************************
// Generate Signal
//-**************************************************************************
   reg          genreg;
   always @(posedge clk or negedge reset_n)
     begin
       if (!reset_n)
         genreg = load_genreg;
       else
         genreg = ~genreg;
       end
   //-**************************************************************************
// Shift register
//-**************************************************************************
   reg   sreg;
   always @(posedge clk)
     begin
*     sreg = sreg;
       sreg   = genreg;
     end
   assign out = sreg;
endmodule