SGDMA with DDR2 and clock crossing

Hi,

I have a project where I collect some streaming data with a stream to mem SGDMA and place it in a ddr2.

I placed a clock crossing bridge between the ddr2 controller and the SGDMA.

Now, when I initiate a transaction with the SGDMA, the descriptor callback is called at the end of the transaction with an end of packet received but the number of transmitted bytes does not match the correct number of data that has been streamed.

Is it possible that the settings of the clock crossing bridge do not allow a correct transmission by the SGDMA?

What are parameters that I should set carefully?

thanks