Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

SGDMA and Shared memory

Hello All,

I'm trying to understand how can I share memory between a nios application and vhdl logic.

I have a DE0 nano board which has an SDRAM I want to use. I can't use only on chip memory to store my nios application code so I need to use a part of the SDRAM.

But, I need the SDRAM too to store stream of data coming from logic. These data need to be written by a logic block, then these data need to be accessible by Nios AND hardware logic block... It's very simple : one SDRAM block for nios application code. All the rest for data storage with access from vhdl logic and nios.

I made many research and it seem's that SGDMA is the answer to do what I want. But I'm not familiar with this and it's pretty difficult for me to understand how to construct my system and how it can works...

Particulary, this topic is really interesting for me because it's exactly the same functionnality I'm trying to do. But no enough information for me to understand what I need to do...

../forum/showthread.php?t=36448

(sorry for the truncated link but as a new member I can't post links...)

Does I need one SGDMA core connecting with my Nios, another SGDMA core connecting in hardware ? Where do I need to write descriptors for nios AND for hardware access ? I find an SGDMA controller in SOPC / Qsys. But how to connect my hardware logic ?

Any help will be appreciate. But please, be as clear as possible because I know nothing about all of these functionnalities.

Many thanks in advance !

Fabrice.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    There are SGDMA examples on Altera Wiki. You can also write Your own DMA, so Avalon-MM interconnect will automatically arbitrate between data streams.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you for your reply Socrates.

    So if I understand correctly :

    - I write a module with an avalon master port which I can control from user logic. Actually, it's an user bus to avalon bridge.

    - I create an new Qsys design with a Nios 2 processor, an SDRAM controller, an SGDMA controller and the new component with its avalon master port.

    - I connect both master port from the nios and the bridge to the SGDMA controller and the output of the DMA to the SDRAM controller.

    And for the hardware, that's all.

    I place reset and execution vector from the nios in the SDRAM.

    I can place DMA request from the nios to the SDRAM.

    I can place DMA request from the user logic to the SDRAM.

    Avalon switch fabric will automaticaly arbitrate between all the DMA request ?

    Am I in the wright direction ?

    Thanks for your help.