SGDMA and Shared memory

Thank you for your reply Socrates.

So if I understand correctly :

- I write a module with an avalon master port which I can control from user logic. Actually, it's an user bus to avalon bridge.

- I create an new Qsys design with a Nios 2 processor, an SDRAM controller, an SGDMA controller and the new component with its avalon master port.

- I connect both master port from the nios and the bridge to the SGDMA controller and the output of the DMA to the SDRAM controller.

And for the hardware, that's all.

I place reset and execution vector from the nios in the SDRAM.

I can place DMA request from the nios to the SDRAM.

I can place DMA request from the user logic to the SDRAM.

Avalon switch fabric will automaticaly arbitrate between all the DMA request ?

Am I in the wright direction ?

Thanks for your help.