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Altera_Forum
Honored Contributor
Honored Contributorsfixed to standard logic vector
is it possible to have sfixed converted to standard logic vector? if yes..how??
i need to use sfixed because the input data are all fractional real number. and the input need to be map to the rom to retrieve its appropriate output. but the address of the rom hav to be in standard logic vector, am i right? so i need to convert the sfixed to standard logic vector.2 Replies
Altera_Forumyeah im using IEEE.fixed_pkg so is the following correct??
signal out: sfixed(3 downto -12); signal outS : std_logic_vector (15 downto 0); out <= obtain_Yn_real(1); outS <= to_StdLogicVector(out, 16);- Altera_Forum
Sounds like your using IEEE.fixed_pkg. It has a conversion function to_slv alias to_StdLogicVector.
