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Altera_Forum
Honored Contributor
Honored Contributorsfixed to standard logic vector
is it possible to have sfixed converted to standard logic vector? if yes..how?? i need to use sfixed because the input data are all fractional real number. and the input need to be map to the r...
Altera_ForumHonored Contributor
Honored ContributorSounds like your using IEEE.fixed_pkg. It has a conversion function to_slv alias to_StdLogicVector.
