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Altera_Forum's avatar
Altera_Forum
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18 years ago

sfixed to standard logic vector

is it possible to have sfixed converted to standard logic vector? if yes..how?? i need to use sfixed because the input data are all fractional real number. and the input need to be map to the r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

yeah im using IEEE.fixed_pkg so is the following correct??

signal out: sfixed(3 downto -12);

signal outS : std_logic_vector (15 downto 0);

out <= obtain_Yn_real(1);

outS <= to_StdLogicVector(out, 16);