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Honored Contributor
Honored ContributorSEU ref. design and map of care/don't care bits
Hello Recently I read a White paper with title Robust SEU Mitigation with StratixIII FPGAs. In this paper, it is said that StratixIII FPGA has a hard logic CRC Engine that employs a 16-bit CR...
Altera_ForumHonored Contributor
Honored ContributorAnswer received from Altera :
I checked in database, there is no such design example on this soft logic "critical error detection". The reference design available on this CRC Error Detection is from the following link: http://www.altera.com/literature/an/an539.pdf http://www.altera.com/literature/an/an539_design_example.zip
