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Altera_Forum's avatar
Altera_Forum
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8 years ago

Setup timing violation

Should I just split the combinatorial logic at line 15 of the following verilog module or https://github.com/promach/internal_logic_analyzer/blob/master/rtl/check_data.v#l15 across several registers ?

https://alteraforum.com/forum/attachment.php?attachmentid=14127&stc=1 

`include "define.v"
module check_data (clk, data_out, data_in, test_failed);  // verifying the memory (circular buffer) read and write processes
input clk;
input  data_out;  // memory output
input  data_in;   // memory input
output reg test_failed = 0;
wire data_out_is_valid;
always @(posedge clk)
begin
    if(((data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY) != (data_in + 1)) && data_out_is_valid)  // due to "delay.v"
    test_failed <= 1;
end
assign data_out_is_valid = (data_in >= `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY) && 
               (data_in < `MEMORY_SIZE + `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY);
endmodule

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Your screen cap is too small to see, but you should certainly perform some of those calculations and comparisons outside of the always block in their own assign statements.

    So you could say

    assign data_out_calc = data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY;

    and do a check of just data_out_calc in the if statement.

    You could also do something similar for the righthand side of the if statement comparison check.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    OK.

    By the way, I found out what went wrong with my setup timing violation. It is due to my mistake in timing constraint xdc file. My system clock is 1Ghz