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Altera_Forum
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17 years ago

Setting up PLL for the DDR Controller Megacore

Hey there ! I have some trouble getting the DDR Controller to work on the Nios Development Board, Cyclone II edition. I am using Quartus II 8.0 SP1, Web Edition. I've started my experiment...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I found a hack to fix this, but I am not sure if I did the right thing. I have Quartus II 10.1 installed under C:\altera\10_1\ So all paths here refer to that base directory. I patched the file C:\altera\10_1\ip\altera\ddr_ddr2_sdram\lib\tcl\paths.tcl In the procedure "extract_clk_tco" there are the lines 


} elseif { $family == "cycloneii" } {
::ddr::extract::follow_edge2 mux async "${basename}\\|ddio_out_...:auto_generated\\|muxa\\\\\\]\$" found_tco "" failflag
::ddr::extract::follow_edge2 mux async "~DELAY_CELL\$" found_tco "" failflag
} elseif { $family == "stratixii" } {
I think the 2nd "::ddr::extract::follow_edge2 mux ..." is wrong so I changed that to 


} elseif { $family == "cycloneii" } {
::ddr::extract::follow_edge2 mux async "${basename}\\|ddio_out_...:auto_generated\\|muxa\\\\\\]\$" found_tco "" failflag#  ::ddr::extract::follow_edge2 mux async "~DELAY_CELL\$" found_tco "" failflag
} elseif { $family == "stratixii" } {
commenting this line out. After that it worked without problems. so long