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Altera_Forum
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7 years ago

Setting up PCIe Connection Cyclone V

Hello, I am trying to set up a Cyclone V FPGA so that I can configure the core image through a PCIe connection. As far as I understand it, I need to create a .periph.jic file to upload to the FPGA fi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Have you try to program the .sof file directly to the Cyclone V via the JTAG successfully? Since you are using the on-board USB Blaster II port, you can try to reduce the TCK frequency in USB Blaster II to 16Mhz or 6Mhz. You can modify the USB Blaster II JTAG frequency with the following command in command prompt:

> jtagconfig --setparam <cable_number> JtagClock <frequency>

where <frequency> is either 6M or 16M.

Since you mentioned that your goal is to have the Cyclone V be visible to the Linux machine that it is connected to through PCIe and don't really care how this happens, you can just program the .sof file directly to the Cyclone V device.

Plug the Cyclone V GT dev kit to your Linux machine PCIe slot. Power up the Cyclone V GT dev kit via its own power adapter via J8 connector. While the power is on, program the .sof file via the J5 connecter (on-board USB Blaster II). Once the .sof file programming is successful (where the Quartus programmer show the success message), power up the Linux machine. Then try to use the lspci command.

Regards,

nyusof

(This message was posted on behalf of Intel Corporation)