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Altera_Forum's avatar
Altera_Forum
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17 years ago

Setting up a 25Mhz PLL

Hi,

I have a PCIe Stratix II dev Kit. I need a 25Mhz clk out. My understanding is that the FPGA can provide a clock out (using the 100 MHz on board internal clock) by setting up a PLL. If this is correct, how do I go about doing it.?

I have no idea on how to set it up. Any help will be appreciated.

Thanks in advance.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    You need to create an ALTPLL instance that will create a PLL in your design. The PLL will accept your 100MHz clock as input and produce a 25MHz clock as output.

    From Quartus II:

    1 - Tools->MegaWizard Plug-In Manager.

    2 -Create a new custom megafunction variation.

    3 - Select the I/O category on the left.

    4 - Then select the ALTPLL megafunction.

    5 - Give your file a name and click next. The megawizard will launch. Read the documentation if you need to. At the end of the day you'll have a verilog or vhdl module that you can instantiate in your design.

    Jake