set_input_delay And set_output_delay .SDC Constraints

You don't look at signal tap or data integrity to check timing constraints as it is the hard way. You better check timequest waveforms on the path(report timing path in the timequest GUI)

I believe from your device diagrams that its data/clock offsets are meant to be same regardless of clock edge. So you configure device to use say rising edge as fpga then use the figures directly.i.e. 9/26 for min/max input delay sdc values & -0.5/+0.5 for min/max output delay sdc values. If timing does not pass it does not mean sdc commands are wrong.