set_input_delay And set_output_delay .SDC Constraints

Hello again! Kaz, I am back with the results and I think I have an obligation to share them with you and everyone else in case they prove to be beneficial.The results seem to contradict what we had established here.Here's what happened :When I configured the external device to output data on the rising edge of the clock with the input delay(min) set to 9ns and the input delay(max) set to 26ns(both w.r.t to rising edge). These are the bytes that were latched on the rising edge, with the input constraints :

Vcd File Exported from Signal Tap, displayed in gtkwave :

https://www.alteraforum.com/forum/attachment.php?attachmentid=13497

Now, when I configure the external device to output data on the falling edge of the clock and remove all sdc constraints, except the clock constraints, I seem to get the correct pattern.These are the bytes that were latched when data was output on the falling edge, sampled on the rising edge, without any Input Constraints :

Signal Tap File

https://www.alteraforum.com/forum/attachment.php?attachmentid=13498

Please note that the correct synchronization pattern is FF 00 00 XYZ.

These results were obtained using the SignalTap Logic Analyzer.The sampling clock for SignalTap is the same as the clock input from the external device(which also clocks the input register).