set_input_delay And set_output_delay .SDC Constraints

I think I might know what's happening here.The two clocks are shown because of the I2C configurable latching(rising edge or falling edge for single latching mechanism).The diagram here shows dual latching (on both rising and falling edges), it basically latches twice per clock cycle, which is why the tS and tH are labelled as they are.I think the diagram just says that in the 1 ns around any edge(0.5 ns for setup and 0.5 ns for hold), the data should remain constant if the dual latching mechanism is used.