set_input_delay And set_output_delay .SDC Constraints

I found this guide by Ryan Scotville and it seems to have done the trick.With your posts here and that guide, I think I now have an understanding of how this works.I realize that the only requirement on the input register is that its setup time should be less than the TCO max of the device and that its hold time must be less than the TCO min. However, I have one final problem that I've run into.While trying to constrain the output side, (which too is at 27Mhz, I seem to have a rather strange result). Please view the attached diagrams. The setup time -minimum value is 0.5 ns.The hold time -minimum value is 0.5 ns, but the Hold Time is described wrt to the falling edge of the clock(Data at output gets latched on the rising edge of the clock).I tried to implement this constraint by setting the minimum output delay to (18.5ns + 0.5ns), but the constraints fail.I have seen you post elsewhere that the min delay should be set to -tH, but that seems to be the case when tS and tH are wrt to the same edge.