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Thank you for your patience!
I think I have something fundamentally wrong.
Let's assume that there are two registers.One is the Input Register, and the other is a simple register somewhere in the design.
Now, when I set the output_delay to 26 ns, I imagine that the Input Register and the other register get clocked differently.
To me, the input register gets its clock pulse at 26, 26 + 37 , 26 + 2*37 ,..........., 26 + n*37......
And the other register is clocked at 37, 37 + 37, 37 + 37.
So, when I think like this, I imagine that whatever combinational logic is inserted between the register that gets clocked at 26, 26 + 37....(Input Register)
and the other register which gets clocked at (37, 37 + 37), has only 37 - 26 = 11 ns to settle.If instead we used back to back registers to just crossover from the input domain to the simple register domain, we'd have the complete 37ns between clock pulses?
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Each register has its own tCO. In your case the external device has tCO max of 26ns and assuming it stays so at fpga pins.
The fpga registers have their own tCO and a fast io register is expected to have its tCO short enough (that is why we say fast io register).
The clock period is 37 ns for all paths clocked by that clock but the window available for sampling is much less on any path because it starts from max tCO moment and ends at tSU restrictions.
The tCO at any register should be as short as possible without hitting back on tH of previous latch edge, and shouldn't be as long as to hit tSU of next latch edge.
The fitter ensures tCO doesn't hit tH as clock is designed always faster than data(this is done at silicon level i.e. fast clock networks).
The tSU will be safe from violation as long as the clock is not too fast or data delay is not too much.
Long combinatorial sections mean more data delay and may violate tSU so either break it up into thinner sections or lower the clock rate.
In short "enter input constraints and check timing of rtl chains in your design and if you run into trouble then you start to help the tool" by pipelining ...etc.
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