set_input_delay And set_output_delay .SDC Constraints

Thank you for your patience!

I think I have something fundamentally wrong.

Let's assume that there are two registers.One is the Input Register, and the other is a simple register somewhere in the design.

Now, when I set the output_delay to 26 ns, I imagine that the Input Register and the other register get clocked differently.

To me, the input register gets its clock pulse at 26, 26 + 37 , 26 + 2*37 ,..........., 26 + n*37......

And the other register is clocked at 37, 37 + 37, 37 + 37.

So, when I think like this, I imagine that whatever combinational logic is inserted between the register that gets clocked at 26, 26 + 37....(Input Register)

and the other register which gets clocked at (37, 37 + 37), has only 37 - 26 = 11 ns to settle.If instead we used back to back registers to just crossover from the input domain to the simple register domain, we'd have the complete 37ns between clock pulses?