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Will the IO register(the one that has to read the value at the input pins) latch this value at t >= 26 ns?
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That is what input path timing pass/fail will tell you. If it passes or fails a second register after io is not going to do any good because that path is a new path that the tool takes care of. So you don't need to visualise what happens at that path, leave it to the tool.if any path in your entire design fails the tool will tell you.
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This scheme is only for the input/output from the FPGA.
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Such scheme is not needed specifically for io. each io needs just one register. a second register can be added (back to back) but is not going to do much for timing. It is not the user responsibility to look after delay figures for internal paths. (only exceptionally one might do chip planning for some difficult paths).
back to back registers have very short routing, pass timing, do nothing apart from latency matching or random effect on overall routing.
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