set_input_delay And set_output_delay .SDC Constraints

I understand the register------>comb------>register part.But, kindly answer me this :

1) Let's say that at t = 0, we have a rising edge on the clock.

2) The external device outputs data at 26ns (TCO max).

3) Question :

Will the IO register(the one that has to read the value at the input pins) latch this value at t >= 26 ns?

If so, this value becomes available in the FPGA at t >= 26ns or (26/37) of the clk period? Would it not be better to add another register(cascade/series) that stores the value at the next rising edge? Doing so would use up one clock cycle though.

This scheme is only for the input/output from the FPGA.

Thank you!