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Hello again!
I was wondering that since my design depends on detecting a pattern initiated when the external device outputs an 8'hFF, if I would not be better off using an additional register (in addition to the IO Register). I figure that if I use a comparator on the IO Register, it would only have 37ns - (26ns + TCO of IO Register) before the next positive clock edge, but if I use one extra register, it would give me nicely aligned data and a complete 37 ns while only increasing the latency by 1. Similarly, when outputting to an external device, one could add a simple register before the Final Fast Output register. In short, is it not better to have something like the following?
For Input :
Input Pins ---------------> IO Register ---------------> Register----------->Design
For Output :
Design------------> Register--------------> IO Register------------> Output Pins
I realize that all this may sound extremely repetitive, but it would go a long way in deepening my understanding if you confirm this.
P.S. (I just have a hard time wrapping my head around how the IO registers get sampled after the TCOmax of the external device).
Thank you!
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you are a bit off track on fpga timing strategy.
The io timing is your responsibility as a user. Beyond that inside fpga the tool takes responsibility of any register chain timing.
Your design will eventually needs register-comb-register chains and that will be managed by tool (and easily for 27MHz).
You are free to use such chains as required for your tasks. The depth of comb section is better kept short so that you achieve timing readily.
Honored Contributor
