set_input_delay And set_output_delay .SDC Constraints

Hello again!

I was wondering that since my design depends on detecting a pattern initiated when the external device outputs an 8'hFF, if I would not be better off using an additional register (in addition to the IO Register). I figure that if I use a comparator on the IO Register, it would only have 37ns - (26ns + TCO of IO Register) before the next positive clock edge, but if I use one extra register, it would give me nicely aligned data and a complete 37 ns while only increasing the latency by 1. Similarly, when outputting to an external device, one could add a simple register before the Final Fast Output register. In short, is it not better to have something like the following?

For Input :

Input Pins ---------------> IO Register ---------------> Register----------->Design

For Output :

Design------------> Register--------------> IO Register------------> Output Pins

I realize that all this may sound extremely repetitive, but it would go a long way in deepening my understanding if you confirm this.

P.S. (I just have a hard time wrapping my head around how the IO registers get sampled after the TCOmax of the external device).

Thank you!