set_input_delay And set_output_delay .SDC Constraints

yes launching external device data on rising edge looks better in your case.

data and clock board delays are unique to your design. if both are equal, same material and thickness then you can ignore it. After all such delays are in picoseconds and if you are not sure you may just add extra margin on your sdc figures to further limit the sampling window e.g. 9/26 instead of 10/25

The theory goes too far to max/min of board delays but this only practically is worth checking in very fast paths.