set_input_delay And set_output_delay .SDC Constraints

Thank you so much!I am especially thankful for the last reply and configuring the IO registers as this was something I didn't even care to ask(and didn't know).

The device is configured via I2C to output data on either rising or falling edge.Initially, I thought that outputting data on the negative edge and sampling it on the positive edge would leave out one half clock cycle for set up time, but this seems to have been wrong.I can configure the device to output data on the rising edge and set min_delay to 10 and max_delay to 25.This should do the trick?

Now, I don't have values for board delay or clock skew.What do you recommend I do to incorporate this uncertainty as well?

Let's assume that board delay = b ns and that clock skew = +-c ns.

Then,

input_delay_min = 10ns + b - c.

input_delay_max = 25ns + b + c.

If the above equations are right, what values do I select for b or c? I apologize if this is something only I can know because I don't have any information about these parameters.