Forum Discussion
Occasional ContributorSerial Flash Loader IP not working with A10 and EPCQL512
When comparing the behavior of the factory SFL image and my design with SFL IP added I still don't understand why the attached serial flash shows up in a JTAG scan with the factory image loaded, and not in a scan when my design is loaded.
However, after deciding to assume that the SFL in my design otherwise works and testing JTAG access to serial flash (such as doing a flash verification operation without having to first load the factory SFL image) the SFL IP does appear to bridge JTAG and ASMI.
I create and load a jic file as usual, then uncheck the box for configuring the factory SFL image prior to flash access. My design remains loaded in the FPGA, and I can verify or load the flash without disturbing FPGA operation.
So it works for my purposes, although with a minor quirk of not being able to detect the flash presence via a scan.
Regular ContributorTo access the flash via JTAG, you will need a controller in the FPGA which i will suggest the usage of SFL IP. Meaning to say, you need to have this IP in your SOF file. Unless, you have a direct connection from JTAG to FLASH without using FPGA. Otherwise, a controller is a must for that.
