New ContributorHello,
I would like to use the SERDES link to test its efficiency on the Cyclone GX development kit.
However, I don't understand how I can use this link in my VHDL program for my FPGA and how I can measure its efficiency and its execution time.
If you can help me on this subject, I will be very grateful. Thanking you.
CHARLES Antoine
Frequent ContributorHi Charles
You can refer to guideline document below for some explanation regarding LVDS and SERDES requirements:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51009.pdf
Unfortunately I couldn't locate any reference design in the database.
Thanks.
Frequent ContributorI am transferring the thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Regards
Eng Wei
